1. Field of the Invention
This invention generally relates to logic circuits used in processing systems.
2. Description of the Related Art
Register elements such as flip-flops and latches are used in microprocessor systems because inter alia they keep signals correlated in time. Modern designs require a large number of register elements. The exact number used depends on factors such as the speed and output load requirements of the implementing circuit. While fast flip-flops and latches enable short-cycle times and perform high-frequency operations, they often consume large amounts of energy. Various methods have been developed to reduce energy consumption by minimizing clocking energy. This may be accomplished by driving the register elements with a reduced-swing clock signal.
Most commonly used high-speed register elements are either based on hybrid latch-flip-flop configurations or pulse-triggered cycle latches. Both types of circuits demonstrate similar delay performance, however cycle latches exhibit lower energy consumption measured at the same delay, as well as better delay measured at the same energy. Cycle latches are clocked with a short pulse at each rising edge of the clock. This provides a short transparency period and requires only one latch per clock cycle. Hence, the name “cycle latch.”
FIG. 1 shows an example of a type of cycle latch known as an explicit-pulsed static flip-flop (ep-SFF). This circuit is a D-type flip-flop which includes a switch 1 and four inverters numbered 2 through 5. The switch is in the form of a transmission gate which contains a parallel connection of an NMOS transistor 6 and a PMOS transistor 7. In operation, the D input is transferred to a node Ss when clock signal Cpulse goes high. More specifically, when Cpulse goes high, the NMOS transistor is switched on and inverter 2 outputs a low signal, which, in turn, activates the PMOS transistor. As a result, the value of the D input is connected to node Ss and the logic value at node Ss is inverted by inverter 5 to output the value of the output.
The circuit formed by the connection of inverters 3 and 4 corresponds to a “keeper structure” which is basically a memory element. This circuit operates as a feedback structure that ensures that whatever value is written to node Ss when the transmission gate is on does not disappear when the transmission gate is turned off For example, if the D input equals a logical zero, node Ss will also be pulled down to zero when the transmission gate turns on. This, in turn, causes node qFB to rise to a logical 1 value, which then feeds back through inverter 3 which again produces a logical zero at node Ss. So, even without the data input connected to node Ss, the value will be maintained. The inverters in the keeper structure may be made very weak (i.e., small transistor sizes) so that they can be overpowered by the transmission gate and therefore the value stored on node Ss can be changed. On the other hand, the inverters are made strong enough so that even if there is leakage on node Ss or qFB, or noise coupled to these nodes from other circuits switching, the stored value will not be corrupted.
FIG. 2 shows a cycle latch circuit which achieves improved energy consumption efficiency over the ep-SFF discussed above. In this circuit, energy consumption is reduced by performing low-swing clock operation, which requires the clocking of one or more NMOS transistors. More specifically, this circuit includes a transistor 10 and a plurality of inverters 11 through 14. The transistor is an NMOS enhancement transistor, that is, one having a positive threshold voltage as used in any standard CMOS process. Inverter 12 is an inverter having an NMOS enable terminal 16 which is controlled by the output of inverter 11. When disabled, inverter 12 prevents the output from discharging to ground. The NMOS transistor is switched by a clock signal Cpulse in order to transfer a D input to a node Ss. This same clock signal is input into inverter 11. Because the clock signal only connects to NMOS transistors, the circuit may be referred to as an NMOS-only-clocked cycle latch.
Operation of the NMOS-only-clocked cycle latch circuit will now be described. When the D input is low and the clock signal Cpulse goes high, storage node Ss goes low and a high logic level is established at node, which is the output of the cycle latch. This is because inverter 14 inverts the low signal level at node Ss to the high logic value. Inverter 11 inverts the high value of Cpulse into a low (or logical 0) value which turns off inverter 12 in the manner previously described. As a result, node Ss assumed a value which corresponds to the D input.
When the D input is high and clock signal Cpulse goes high, CN goes low and the pull-down of inverter 11 is disabled. At the same time, the high level of the D input propagates to the latch storage node Ss. Inverter 13 pulls down node qFB which in turn helps pull up node Ss to a full swing as a result of the inversion operation performed by inverter 12. More specifically, inverter 13 outputs a low level which pulls node qFB down to a low level. This low-level signal is then inverted by inverter 12, which outputs a high-level signal which pulls up the voltage at node Ss to full swing. This high logical level at node Ss is inverted by inverter 14 to a low logic level, which represents the output of the circuit.
The circuit formed by inverters 12 and 13 operates as a storage element for the circuit and operates in a manner similar to the keeper structure described in FIG. 1. Since storage node Ss is not immediately pulled up to a full swing, the rising transition at the D input takes a delay time to propagate to the output. The circuit of FIG. 2 may also perform low-swing clock operation that allows the circuit to become more energy efficient than the ep-SFF cycle latch discussed above. Low-swing operation refers to the case where the clock voltage Cpulse does not have to be equal to the supply voltage Vcc. For example, the supply voltage may be 1.2 V (supplying the inverters and other circuits on the chip) while the clock voltage may only be 0.6 V. The flip-flop will still work if the clock voltage is lower than supply voltage Vcc (low-swing), but the design in FIG. 1 will not. It is therefore clear that low-swing operation will allows the FIG. 2 circuit to achieve reduced energy consumption since energy is a function of voltage.
While the NMOS-only clocked cycle latch outperforms the ep-SFF circuit in terms of energy efficiency, it also has a number of drawbacks. For example, the NMOS-only circuit demonstrates very slow delay and thus has proven less robust than is desired in many modern applications. The reason for the slow delay may be attributed to the use of a single NMOS transistor as an input pass gate, rather than a full transmission gate 10 (i.e., one constructed from NMOS and PMOS transistors) as shown in FIG. 1. NMOS transistors such as transistor 10 perform well when transferring a logical level of 0 (when the D input=0), but are very slow when transferring a logical level of 1 (when the D input=1). In fact, if the D input is at supply voltage Vcc and NMOS pass gate 10 turned on, node Ss will only rise up to a value of Vcc−Vtn before the transistor turns off (Vtn=threshold voltage of the NMOS transistor.) In order to get node Ss to rise all the way to Vcc, the keeper inverter 12 must pull it up the rest of the way. As a result, the flip-flop circuit performs very slowly when the data input is logical 1.